Index: local-src/contrib/llvm/tools/lld/ELF/InputSection.cpp =================================================================== --- local-src.orig/contrib/llvm/tools/lld/ELF/InputSection.cpp +++ local-src/contrib/llvm/tools/lld/ELF/InputSection.cpp @@ -608,26 +608,40 @@ static int64_t getTlsTpOffset(const Symb if (&s == ElfSym::tlsModuleBase) return 0; + // There are 2 TLS layouts. Among targets we support, x86 uses TLS Variant 2 + // while most others use Variant 1. At run time TP will be aligned to p_align. + + // Variant 1. TP will be followed by an optional gap (which is the size of 2 + // pointers on ARM/AArch64, 0 on other targets), followed by alignment + // padding, then the static TLS blocks. The alignment padding is added so that + // (TP + gap + padding) is congruent to p_vaddr modulo p_align. + // + // Variant 2. Static TLS blocks, followed by alignment padding are placed + // before TP. The alignment padding is added so that (TP - padding - + // p_memsz) is congruent to p_vaddr modulo p_align. + elf::PhdrEntry *tls = Out::tlsPhdr; + switch (config->emachine) { + // Variant 1. case EM_ARM: case EM_AARCH64: - // Variant 1. The thread pointer points to a TCB with a fixed 2-word size, - // followed by a variable amount of alignment padding, followed by the TLS - // segment. - return s.getVA(0) + alignTo(config->wordsize * 2, Out::tlsPhdr->p_align); - case EM_386: - case EM_X86_64: - // Variant 2. The TLS segment is located just before the thread pointer. - return s.getVA(0) - alignTo(Out::tlsPhdr->p_memsz, Out::tlsPhdr->p_align); + return s.getVA(0) + config->wordsize * 2 + + ((tls->p_vaddr - config->wordsize * 2) & (tls->p_align - 1)); + case EM_MIPS: case EM_PPC: case EM_PPC64: - // The thread pointer points to a fixed offset from the start of the - // executable's TLS segment. An offset of 0x7000 allows a signed 16-bit - // offset to reach 0x1000 of TCB/thread-library data and 0xf000 of the - // program's TLS segment. - return s.getVA(0) - 0x7000; + // Adjusted Variant 1. TP is placed with a displacement of 0x7000, which is + // to allow a signed 16-bit offset to reach 0x1000 of TCB/thread-library + // data and 0xf000 of the program's TLS segment. + return s.getVA(0) + (tls->p_vaddr & (tls->p_align - 1)) - 0x7000; case EM_RISCV: - return s.getVA(0); + return s.getVA(0) + (tls->p_vaddr & (tls->p_align - 1)); + + // Variant 2. + case EM_386: + case EM_X86_64: + return s.getVA(0) - tls->p_memsz - + ((-tls->p_vaddr - tls->p_memsz) & (tls->p_align - 1)); default: llvm_unreachable("unhandled Config->EMachine"); } Index: local-src/contrib/llvm/tools/lld/ELF/Writer.cpp =================================================================== --- local-src.orig/contrib/llvm/tools/lld/ELF/Writer.cpp +++ local-src/contrib/llvm/tools/lld/ELF/Writer.cpp @@ -2208,21 +2208,64 @@ void Writer::addPhdrForSection(Par part.phdrs.push_back(entry); } -// The first section of each PT_LOAD, the first section in PT_GNU_RELRO and the -// first section after PT_GNU_RELRO have to be page aligned so that the dynamic -// linker can set the permissions. +// Place the first section of each PT_LOAD to a different page (of maxPageSize). +// This is achieved by assigning an alignment expression to addrExpr of each +// such section. template void Writer::fixSectionAlignments() { - auto pageAlign = [](OutputSection *cmd) { - if (cmd && !cmd->addrExpr) - cmd->addrExpr = [=] { - return alignTo(script->getDot(), config->maxPageSize); - }; + const PhdrEntry *prev; + auto pageAlign = [&](const PhdrEntry *p) { + OutputSection *cmd = p->firstSec; + if (cmd && !cmd->addrExpr) { + // Prefer advancing to align(dot, maxPageSize) + dot%maxPageSize to avoid + // padding in the file contents. + // + // When -z separate-code is used we must not have any overlap in pages + // between an executable segment and a non-executable segment. We align to + // the next maximum page size boundary on transitions between executable + // and non-executable segments. + // + // TODO Enable this technique on all targets. + bool enable = config->emachine == EM_PPC64; + + if (!enable || (config->zSeparateCode && prev && + (prev->p_flags & PF_X) != (p->p_flags & PF_X))) + cmd->addrExpr = [] { + return alignTo(script->getDot(), config->maxPageSize); + }; + // PT_TLS is at the start of the first RW PT_LOAD. If `p` includes PT_TLS, + // it must be the RW. Align to p_align(PT_TLS) to make sure + // p_vaddr(PT_LOAD)%p_align(PT_LOAD) = 0. Otherwise, if + // sh_addralign(.tdata) < sh_addralign(.tbss), we will set p_align(PT_TLS) + // to sh_addralign(.tbss), while p_vaddr(PT_TLS)=p_vaddr(PT_LOAD) may not + // be congruent to 0 modulo p_align(PT_TLS). + // + // Technically this is not required, but as of 2019, some dynamic loaders + // don't handle p_vaddr%p_align != 0 correctly, e.g. glibc (i386 and + // x86-64) doesn't make runtime address congruent to p_vaddr modulo + // p_align for dynamic TLS blocks (PR/24606), FreeBSD rtld has the same + // bug, musl (TLS Variant 1 architectures) before 1.1.23 handled TLS + // blocks correctly. We need to keep the workaround for a while. + else if (Out::tlsPhdr && Out::tlsPhdr->firstSec == p->firstSec) + cmd->addrExpr = [] { + return alignTo(script->getDot(), config->maxPageSize) + + alignTo(script->getDot() % config->maxPageSize, + Out::tlsPhdr->p_align); + }; + else + cmd->addrExpr = [] { + return alignTo(script->getDot(), config->maxPageSize) + + script->getDot() % config->maxPageSize; + }; + } }; for (Partition &part : partitions) { + prev = nullptr; for (const PhdrEntry *p : part.phdrs) - if (p->p_type == PT_LOAD && p->firstSec) - pageAlign(p->firstSec); + if (p->p_type == PT_LOAD && p->firstSec) { + pageAlign(p); + prev = p; + } } } @@ -2350,10 +2393,11 @@ template void Writer: p->p_align = std::max(p->p_align, config->maxPageSize); } else if (p->p_type == PT_GNU_RELRO) { p->p_align = 1; - // The glibc dynamic loader rounds the size down, so we need to round up + // musl/glibc ld.so rounds the size down, so we need to round up // to protect the last page. This is a no-op on FreeBSD which always // rounds up. - p->p_memsz = alignTo(p->p_memsz, config->commonPageSize); + p->p_memsz = alignTo(p->p_offset + p->p_memsz, config->commonPageSize) - + p->p_offset; } } }