diff --git a/hw/nx-crypto.c b/hw/nx-crypto.c index 8b8ff5ee..47617d00 100644 --- a/hw/nx-crypto.c +++ b/hw/nx-crypto.c @@ -13,8 +13,8 @@ #include /* Configuration settings */ -#define CFG_SYM_FC_ENABLE (0) /* disable all sym functions */ -#define CFG_SYM_ENABLE (0) /* disable sym engines */ +#define CFG_SYM_FC_ENABLE (1) /* enable all sym functions */ +#define CFG_SYM_ENABLE (1) /* enable sym engines */ #define CFG_ASYM_FC_ENABLE (0) /* disable all asym functions */ #define CFG_ASYM_ENABLE (0) /* disable asym engines */ #define CFG_CRB_IQ_SYM (0) /* don't use any extra input queues */ @@ -33,10 +33,10 @@ #define EE_CH6 (0) /* disable engine AMF 2(P8) */ #define EE_CH5 (0) /* disable engine AMF 1(P8) */ #define EE_CH4 (0) /* disable engine SYM AMF 0(P8) */ -#define EE_CH3 (0) /* disable engine SYM 1 */ -#define EE_CH2 (0) /* disable engine SYM 0 */ +#define EE_CH3 (1) /* enable engine SYM 1 */ +#define EE_CH2 (1) /* enable engine SYM 0 */ -static int nx_cfg_sym(u32 gcid, u64 xcfg) +static int nx_cfg_crypto_sym(u32 gcid, u64 xcfg) { u64 cfg, ci, ct; int rc, instance = gcid + 1; @@ -92,7 +92,7 @@ static int nx_cfg_sym(u32 gcid, u64 xcfg) return rc; } -static int nx_cfg_asym(u32 gcid, u64 xcfg) +static int nx_cfg_crypto_asym(u32 gcid, u64 xcfg) { u64 cfg, ci, ct; int rc, instance = gcid + 1; @@ -149,7 +149,35 @@ static int nx_cfg_asym(u32 gcid, u64 xcfg) return rc; } -static int nx_cfg_dma(u32 gcid, u64 xcfg) +static int nx_cfg_crypto_umac(struct dt_node *node, u32 gcid, u32 pb_base) +{ + int rc; + u64 umac_bar, umac_notify; + struct dt_node *nx_node; + static u32 nxcrypto_tid = 1; /* tid counter within coprocessor type */ + + nx_node = dt_new(node, "ibm,sym-high-fifo"); + umac_bar = pb_base + NX_P9_SYM_HIGH_PRI_RX_FIFO_BAR; + umac_notify = pb_base + NX_P9_SYM_HIGH_PRI_RX_FIFO_NOTIFY_MATCH; + + rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-sym", "High", gcid, + NX_CT_GZIP, nxcrypto_tid++, umac_bar, + umac_notify); + if (rc) + return rc; + + nx_node = dt_new(node, "ibm,sym-normal-fifo"); + umac_bar = pb_base + NX_P9_SYM_NORMAL_PRI_RX_FIFO_BAR; + umac_notify = pb_base + NX_P9_SYM_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH; + + rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-sym", "Normal", gcid, + NX_CT_GZIP, nxcrypto_tid++, umac_bar, + umac_notify); + + return rc; +} + +static int nx_cfg_crypto_dma(u32 gcid, u64 xcfg) { u64 cfg; int rc; @@ -163,25 +191,27 @@ static int nx_cfg_dma(u32 gcid, u64 xcfg) cfg = SETFIELD(NX_DMA_CFG_AES_SHA_MAX_RR, cfg, AES_SHA_MAX_RR); - cfg = SETFIELD(NX_DMA_CFG_AES_SHA_CSB_WR, cfg, - AES_SHA_CSB_WR); - cfg = SETFIELD(NX_DMA_CFG_AES_SHA_COMPLETION_MODE, cfg, - AES_SHA_COMPLETION_MODE); - cfg = SETFIELD(NX_DMA_CFG_AES_SHA_CPB_WR, cfg, - AES_SHA_CPB_WR); - cfg = SETFIELD(NX_DMA_CFG_AES_SHA_OUTPUT_DATA_WR, cfg, - AES_SHA_OUTPUT_DATA_WR); - - cfg = SETFIELD(NX_DMA_CFG_AMF_MAX_RR, cfg, - AMF_MAX_RR); - cfg = SETFIELD(NX_DMA_CFG_AMF_CSB_WR, cfg, - AMF_CSB_WR); - cfg = SETFIELD(NX_DMA_CFG_AMF_COMPLETION_MODE, cfg, - AMF_COMPLETION_MODE); - cfg = SETFIELD(NX_DMA_CFG_AMF_CPB_WR, cfg, - AMF_CPB_WR); - cfg = SETFIELD(NX_DMA_CFG_AMF_OUTPUT_DATA_WR, cfg, - AMF_OUTPUT_DATA_WR); + if (proc_gen < proc_gen_p9) { + cfg = SETFIELD(NX_DMA_CFG_AES_SHA_CSB_WR, cfg, + AES_SHA_CSB_WR); + cfg = SETFIELD(NX_DMA_CFG_AES_SHA_COMPLETION_MODE, cfg, + AES_SHA_COMPLETION_MODE); + cfg = SETFIELD(NX_DMA_CFG_AES_SHA_CPB_WR, cfg, + AES_SHA_CPB_WR); + cfg = SETFIELD(NX_DMA_CFG_AES_SHA_OUTPUT_DATA_WR, cfg, + AES_SHA_OUTPUT_DATA_WR); + + cfg = SETFIELD(NX_DMA_CFG_AMF_MAX_RR, cfg, + AMF_MAX_RR); + cfg = SETFIELD(NX_DMA_CFG_AMF_CSB_WR, cfg, + AMF_CSB_WR); + cfg = SETFIELD(NX_DMA_CFG_AMF_COMPLETION_MODE, cfg, + AMF_COMPLETION_MODE); + cfg = SETFIELD(NX_DMA_CFG_AMF_CPB_WR, cfg, + AMF_CPB_WR); + cfg = SETFIELD(NX_DMA_CFG_AMF_OUTPUT_DATA_WR, cfg, + AMF_OUTPUT_DATA_WR); + } rc = xscom_write(gcid, xcfg, cfg); if (rc) @@ -193,7 +223,7 @@ static int nx_cfg_dma(u32 gcid, u64 xcfg) return rc; } -static int nx_cfg_iq(u32 gcid, u64 xcfg) +static int nx_cfg_crypto_iq(u32 gcid, u64 xcfg) { u64 cfg; int rc; @@ -218,7 +248,7 @@ static int nx_cfg_iq(u32 gcid, u64 xcfg) return rc; } -static int nx_cfg_ee(u32 gcid, u64 xcfg) +static int nx_cfg_crypto_ee(u32 gcid, u64 xcfg) { u64 cfg; int rc; @@ -230,10 +260,12 @@ static int nx_cfg_ee(u32 gcid, u64 xcfg) return rc; } - cfg = SETFIELD(NX_EE_CFG_CH7, cfg, EE_CH7); - cfg = SETFIELD(NX_EE_CFG_CH6, cfg, EE_CH6); - cfg = SETFIELD(NX_EE_CFG_CH5, cfg, EE_CH5); - cfg = SETFIELD(NX_EE_CFG_CH4, cfg, EE_CH4); + if (proc_gen < proc_gen_p9) { + cfg = SETFIELD(NX_EE_CFG_CH7, cfg, EE_CH7); + cfg = SETFIELD(NX_EE_CFG_CH6, cfg, EE_CH6); + cfg = SETFIELD(NX_EE_CFG_CH5, cfg, EE_CH5); + cfg = SETFIELD(NX_EE_CFG_CH4, cfg, EE_CH4); + } cfg = SETFIELD(NX_EE_CFG_CH3, cfg, EE_CH3); cfg = SETFIELD(NX_EE_CFG_CH2, cfg, EE_CH2); @@ -247,17 +279,31 @@ static int nx_cfg_ee(u32 gcid, u64 xcfg) return rc; } -void nx_create_crypto_node(struct dt_node *node) +static int p9_nx_cfg_crypto_ee(u32 gcid, u64 xcfg) { - u32 gcid; - u32 pb_base; - u64 cfg_dma, cfg_sym, cfg_asym, cfg_iq, cfg_ee; + u64 cfg; int rc; - gcid = dt_get_chip_id(node); - pb_base = dt_get_address(node, 0, NULL); + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; - prlog(PR_INFO, "NX%d: Crypto at 0x%x\n", gcid, pb_base); + cfg = SETFIELD(NX_P9_EE_CFG_CH4, cfg, EE); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +static void nx_enable_crypto(struct dt_node *node, u32 gcid, u32 pb_base) +{ + u64 cfg_dma, cfg_sym, cfg_asym, cfg_iq, cfg_ee; + int rc; if (dt_node_is_compatible(node, "ibm,power8-nx")) { cfg_dma = pb_base + NX_P8_DMA_CFG; @@ -265,34 +311,72 @@ void nx_create_crypto_node(struct dt_node *node) cfg_asym = pb_base + NX_P8_ASYM_CFG; cfg_iq = pb_base + NX_P8_CRB_IQ; cfg_ee = pb_base + NX_P8_EE_CFG; - } else if (dt_node_is_compatible(node, "ibm,power9-nx")) { - prlog(PR_INFO, "NX%d: POWER9 nx-crypto not yet supported\n", - gcid); - return; } else { prerror("NX%d: ERROR: Unknown NX type!\n", gcid); return; } - rc = nx_cfg_dma(gcid, cfg_dma); + rc = nx_cfg_crypto_dma(gcid, cfg_dma); + if (rc) + return; + + rc = nx_cfg_crypto_sym(gcid, cfg_sym); + if (rc) + return; + + rc = nx_cfg_crypto_asym(gcid, cfg_asym); if (rc) return; - rc = nx_cfg_sym(gcid, cfg_sym); + rc = nx_cfg_crypto_iq(gcid, cfg_iq); if (rc) return; - rc = nx_cfg_asym(gcid, cfg_asym); + rc = nx_cfg_crypto_ee(gcid, cfg_ee); if (rc) return; +} - rc = nx_cfg_iq(gcid, cfg_iq); +static void p9_nx_enable_crypto(struct dt_node *node, u32 gcid, u32 pb_base) +{ + u64 cfg_dma, cfg_sym, cfg_ee; + int rc; + + cfg_dma = pb_base + NX_P9_DMA_CFG; + cfg_ee = pb_base + NX_P9_EE_CFG; + + rc = nx_cfg_crypto_dma(gcid, cfg_dma); if (rc) return; - rc = nx_cfg_ee(gcid, cfg_ee); + rc = nx_cfg_crypto_umac(node, gcid, pb_base); if (rc) return; - prlog(PR_INFO, "NX%d: Crypto Coprocessors Disabled (not supported)\n", gcid); + rc = nx_cfg_crypto_ee(gcid, cfg_ee); + ir (rc) + return; + + prlog(PR_INFO, "NX%d: Crypto Coprocessor Enabled\n", gcid); +} + +void nx_create_crypto_node(struct dt_node *node) +{ + u32 gcid; + u32 pb_base; + int rc; + + gcid = dt_get_chip_id(node); + pb_base = dt_get_address(node, 0, NULL); + + prlog(PR_INFO, "NX%d: Crypto at 0x%x\n", gcid, pb_base); + + if (dt_node_is_compatible(node, "ibm,power9-nx")) { + /* @todo We are depending on the umac setup being done for us + * already. It currently lives in nx_create_compress_node() + * but should live a level up in the main nx.c! + */ + p9_nx_enable_crypto(node, gcid, pb_base); + } else + nx_enable_crypto(node, gcid, pb_base); } diff --git a/hw/nx.c b/hw/nx.c index 12204808..cdfc0f52 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -101,9 +101,9 @@ static void nx_init_one(struct dt_node *node) if (!vas_nx_enabled()) return; - nx_create_crypto_node(node); - nx_create_compress_node(node); + + nx_create_crypto_node(node); } void nx_init(void) diff --git a/include/nx.h b/include/nx.h index 5734e24a..e4c0cae5 100644 --- a/include/nx.h +++ b/include/nx.h @@ -62,31 +62,32 @@ #define NX_DMA_CFG_842_COMPRESS_PREFETCH PPC_BIT(23) #define NX_DMA_CFG_842_DECOMPRESS_PREFETCH PPC_BIT(24) #define NX_DMA_CFG_AES_SHA_MAX_RR PPC_BITMASK(25, 28) -#define NX_DMA_CFG_AMF_MAX_RR PPC_BITMASK(29, 32) +#define NX_DMA_CFG_AMF_MAX_RR PPC_BITMASK(29, 32) /* P8 */ #define NX_DMA_CFG_842_COMPRESS_MAX_RR PPC_BITMASK(33, 36) #define NX_DMA_CFG_842_DECOMPRESS_MAX_RR PPC_BITMASK(37, 40) -#define NX_DMA_CFG_AES_SHA_CSB_WR PPC_BITMASK(41, 42) -#define NX_DMA_CFG_AES_SHA_COMPLETION_MODE PPC_BITMASK(43, 44) -#define NX_DMA_CFG_AES_SHA_CPB_WR PPC_BITMASK(45, 46) -#define NX_DMA_CFG_AES_SHA_OUTPUT_DATA_WR PPC_BIT(47) -#define NX_DMA_CFG_AMF_CSB_WR PPC_BITMASK(49, 50) -#define NX_DMA_CFG_AMF_COMPLETION_MODE PPC_BITMASK(51, 52) -#define NX_DMA_CFG_AMF_CPB_WR PPC_BITMASK(53, 54) -#define NX_DMA_CFG_AMF_OUTPUT_DATA_WR PPC_BIT(55) +#define NX_DMA_CFG_AES_SHA_CSB_WR PPC_BITMASK(41, 42) /* P8 */ +#define NX_DMA_CFG_AES_SHA_COMPLETION_MODE PPC_BITMASK(43, 44) /* P8 */ +#define NX_DMA_CFG_AES_SHA_CPB_WR PPC_BITMASK(45, 46) /* P8 */ +#define NX_DMA_CFG_AES_SHA_OUTPUT_DATA_WR PPC_BIT(47) /* P8 */ +#define NX_DMA_CFG_AES_SHA_CPB_CHECK PPC_BIT(48) /* P9 */ +#define NX_DMA_CFG_AMF_CSB_WR PPC_BITMASK(49, 50) /* P8 */ +#define NX_DMA_CFG_AMF_COMPLETION_MODE PPC_BITMASK(51, 52) /* P8 */ +#define NX_DMA_CFG_AMF_CPB_WR PPC_BITMASK(53, 54) /* P8 */ +#define NX_DMA_CFG_AMF_OUTPUT_DATA_WR PPC_BIT(55) /* P8 */ #define NX_DMA_CFG_842_SPBC PPC_BIT(56) -#define NX_DMA_CFG_842_CSB_WR PPC_BITMASK(57, 58) -#define NX_DMA_CFG_842_COMPLETION_MODE PPC_BITMASK(59, 60) -#define NX_DMA_CFG_842_CPB_WR PPC_BITMASK(61, 62) -#define NX_DMA_CFG_842_OUTPUT_DATA_WR PPC_BIT(63) +#define NX_DMA_CFG_842_CSB_WR PPC_BITMASK(57, 58) /* P8 */ +#define NX_DMA_CFG_842_COMPLETION_MODE PPC_BITMASK(59, 60) /* P8 */ +#define NX_DMA_CFG_842_CPB_WR PPC_BITMASK(61, 62) /* P8 */ +#define NX_DMA_CFG_842_OUTPUT_DATA_WR PPC_BIT(63) /* P8 */ /* Engine Enable Register */ #define NX_P8_EE_CFG NX_P8_SAT(0x1, 0x01) #define NX_P9_EE_CFG NX_P9_SAT(0x1, 0x01) #define NX_EE_CFG_EFUSE PPC_BIT(0) -#define NX_EE_CFG_CH7 PPC_BIT(53) /* AMF */ -#define NX_EE_CFG_CH6 PPC_BIT(54) /* AMF */ -#define NX_EE_CFG_CH5 PPC_BIT(55) /* AMF */ -#define NX_EE_CFG_CH4 PPC_BIT(56) /* AMF */ +#define NX_EE_CFG_CH7 PPC_BIT(53) /* AMF (P8) */ +#define NX_EE_CFG_CH6 PPC_BIT(54) /* AMF (P8) */ +#define NX_EE_CFG_CH5 PPC_BIT(55) /* AMF (P8) */ +#define NX_EE_CFG_CH4 PPC_BIT(56) /* AMF (P8) */ #define NX_EE_CFG_CH3 PPC_BIT(57) /* SYM */ #define NX_EE_CFG_CH2 PPC_BIT(58) /* SYM */ #define NX_P9_EE_CFG_CH4 PPC_BIT(61) /* gzip */ @@ -95,6 +96,7 @@ /* Max byte count register - P9 and later */ #define NX_P9_842_MAX_BYTE_COUNT NX_P9_SAT(0x1, 0x19) +#define NX_P9_SYM_MAX_BYTE_COUNT NX_P9_SAT(0x1, 0x1a) #define NX_P9_GZIP_MAX_BYTE_COUNT NX_P9_SAT(0x1, 0x1b) #define NX_P9_DMA_VAS_MMIO_BAR NX_P9_SAT(0x1, 0x1e) @@ -107,15 +109,19 @@ /* UMAC registers - P9 and later */ #define NX_P9_842_HIGH_PRI_RX_FIFO_BAR NX_P9_SAT(0x3, 0x00) +#define NX_P9_SYM_HIGH_PRI_RX_FIFO_BAR NX_P9_SAT(0x3, 0x01) #define NX_P9_GZIP_HIGH_PRI_RX_FIFO_BAR NX_P9_SAT(0x3, 0x02) #define NX_P9_842_NORMAL_PRI_RX_FIFO_BAR NX_P9_SAT(0x3, 0x09) +#define NX_P9_SYM_NORMAL_PRI_RX_FIFO_BAR NX_P9_SAT(0x3, 0x0a) #define NX_P9_GZIP_NORMAL_PRI_RX_FIFO_BAR NX_P9_SAT(0x3, 0x0b) #define NX_P9_RX_FIFO_BAR_ADDR PPC_BITMASK(8, 53) #define NX_P9_RX_FIFO_BAR_SIZE PPC_BITMASK(54, 56) #define NX_P9_842_HIGH_PRI_RX_FIFO_NOTIFY_MATCH NX_P9_SAT(0x3, 0x06) +#define NX_P9_SYM_HIGH_PRI_RX_FIFO_NOTIFY_MATCH NX_P9_SAT(0x3, 0x07) #define NX_P9_GZIP_HIGH_PRI_RX_FIFO_NOTIFY_MATCH NX_P9_SAT(0x3, 0x08) #define NX_P9_842_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH NX_P9_SAT(0x3, 0x0f) +#define NX_P9_SYM_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH NX_P9_SAT(0x3, 0x10) #define NX_P9_GZIP_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH NX_P9_SAT(0x3, 0x11) #define NX_P9_RX_FIFO_NOTIFY_MATCH_LPID PPC_BITMASK(4, 15) #define NX_P9_RX_FIFO_NOTIFY_MATCH_PID PPC_BITMASK(20, 39) @@ -123,8 +129,10 @@ #define NX_P9_RX_FIFO_NOTIFY_MATCH_MATCH_ENABLE PPC_BIT(63) #define NX_P9_842_HIGH_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x03) +#define NX_P9_SYM_HIGH_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x04) #define NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x05) #define NX_P9_842_NORMAL_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x0c) +#define NX_P9_SYM_NORMAL_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x0d) #define NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x0e) #define NX_P9_RX_FIFO_CTRL_READ_OFFSET PPC_BITMASK(4, 11) #define NX_P9_RX_FIFO_CTRL_QUEUED PPC_BITMASK(15, 23) @@ -151,9 +159,9 @@ #define NX_STATUS_DMA_CH2_IDLE PPC_BIT(58) #define NX_STATUS_DMA_CH3_IDLE PPC_BIT(59) #define NX_STATUS_DMA_CH4_IDLE PPC_BIT(60) -#define NX_STATUS_DMA_CH5_IDLE PPC_BIT(61) -#define NX_STATUS_DMA_CH6_IDLE PPC_BIT(62) -#define NX_STATUS_DMA_CH7_IDLE PPC_BIT(63) +#define NX_STATUS_DMA_CH5_IDLE PPC_BIT(61) /* P8 */ +#define NX_STATUS_DMA_CH6_IDLE PPC_BIT(62) /* P8 */ +#define NX_STATUS_DMA_CH7_IDLE PPC_BIT(63) /* P8 */ /* Channel Status Registers */ #define NX_P8_CH_CRB(ch) NX_P8_SAT(0x1, 0x03 + ((ch) * 2))