diff --git a/sys/powerpc/aim/trap_subr64.S b/sys/powerpc/aim/trap_subr64.S index c3cec9f3ce7..8a1d35b680f 100644 --- a/sys/powerpc/aim/trap_subr64.S +++ b/sys/powerpc/aim/trap_subr64.S @@ -48,17 +48,6 @@ ori r,r,TRAP_TOCBASE; /* Magic address for TOC */ \ ld r,0(r) -/* - * 8 bytes - Load DMAP address 0 into a register. - * Setup for accessing trap area memory with the MMU on or off. - * Optimized for low instruction count instead of flexibility. - * Note: This assumes the least significant 48 bits of - * DMAP_BASE_ADDRESS are 0! - */ -#define DMAP_ZERO(r) \ - lis r,DMAP_BASE_ADDRESS@highesta; /* To real-mode alias/dmap */ \ - sldi r,r,32 - /* * Restore SRs for a pmap * @@ -328,32 +317,29 @@ CNAME(rstcode): * processor is waking up from power saving mode * It is software reset when 46:47 = 0b00 */ - xor %r2,%r2,%r2 /* 0x100 Zero r2 for REAL-MODE idx - * to save one instruction. - */ - ld %r2,TRAP_GENTRAP(%r2) /* 0x104 Establish known location in + ld %r2,TRAP_GENTRAP(0) /* 0x100 Establish known location in * trap_gentrap.S for branch calc. */ - mfsrr1 %r9 /* 0x108 Load SRR1 into r9 */ - andis. %r9,%r9,0x3 /* 0x10c Logic AND with 46:47 bits */ + mfsrr1 %r9 /* 0x104 Load SRR1 into r9 */ + andis. %r9,%r9,0x3 /* 0x108 Logic AND with 46:47 bits */ - beq 2f /* 0x110 Branch if software reset */ + beq 2f /* 0x10c Branch if software reset */ addi %r9,%r2,(cpu_wakeup_handler-generictrap) /* 0x114 */ - b 1f /* 0x118 */ + b 1f /* 0x110 */ /* It is software reset */ /* Explicitly set MSR[SF] */ -2: mfmsr %r9 /* 0x11c */ - li %r8,1 /* 0x120 */ - insrdi %r9,%r8,1,0 /* 0x124 */ - mtmsrd %r9 /* 0x128 */ - isync /* 0x12c */ +2: mfmsr %r9 /* 0x114 */ + li %r8,1 /* 0x118 */ + insrdi %r9,%r8,1,0 /* 0x11c */ + mtmsrd %r9 /* 0x120 */ + isync /* 0x124 */ - addi %r9,%r2,(cpu_reset_handler-generictrap) /* 0x130 */ + addi %r9,%r2,(cpu_reset_handler-generictrap) /* 0x128 */ -1: mtlr %r9 /* 0x134 */ - blr /* 0x138 */ +1: mtlr %r9 /* 0x12c */ + blr /* 0x130 Branch to cpu_reset_handler */ CNAME(rstcodeend): cpu_reset_handler: @@ -473,53 +459,59 @@ CNAME(hypertrapcode): addi %r1,%r1,(generichypertrap-generictrap) mtlr %r1 li %r1, 0xe0 /* How to get the vector from LR */ - blrl /* Branch to generictrap */ + blrl /* Branch to generichypertrap */ CNAME(hypertrapcodeend): /* * For SLB misses: do special things for the kernel * - * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is + * Note: SPRG1 is always safe to overwrite any time the MMU was on, which is * the only time this can be called. */ .globl CNAME(slbtrap),CNAME(slbtrapend) .p2align 3 CNAME(slbtrap): /* 0x00 */ - mtsprg1 %r1 /* save SP */ + mtsprg1 %r1 /* Save r1 (SP) */ GET_CPUINFO(%r1) - std %r2,(PC_SLBSAVE+16)(%r1) - mfcr %r2 /* save CR */ + std %r2,(PC_SLBSAVE+16)(%r1) /* Save r2 */ + mfcr %r2 /* 0x10 */ - std %r2,(PC_SLBSAVE+104)(%r1) - mfsrr1 %r2 /* test kernel mode */ + std %r2,(PC_SLBSAVE+104)(%r1) /* Save CR */ + mfsrr1 %r2 /* Test kernel mode */ mtcr %r2 - bf 17,2f /* branch if PSL_PR is false */ + bf 17,2f /* Branch if PSL_PR is false */ /* 0x20 */ /* User mode */ - ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ - mtcr %r2 - ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */ - mflr %r1 /* Save the old LR in r1 */ + ld %r2,(PC_SLBSAVE+104)(%r1) + mtcr %r2 /* Restore CR */ + ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore r2 */ + mflr %r1 /* 0x30 */ - mtsprg2 %r1 /* And then in SPRG2 */ - DMAP_ZERO(%r1) /* two instructions */ - ld %r1,TRAP_GENTRAP(%r1) - /* 0x40 */ + mtsprg2 %r1 /* Save LR in SPRG2 */ + ld %r1,TRAP_GENTRAP(0) /* Real-mode &generictrap */ mtlr %r1 - li %r1, 0x80 /* How to get the vector from LR */ - blrl /* Branch to generictrap */ -2: mflr %r2 /* Save the old LR in r2 */ - /* 0x50 */ - DMAP_ZERO(%r1) /* two instructions */ - ld %r1,TRAP_GENTRAP(%r1) + li %r1, 0x80 /* LR-to-trap-vector mask */ + /* 0x40 */ + blrl /* Branch to generictrap */ +2: mflr %r2 /* Save LR in r2 */ + /* Kernel mode */ + ld %r1,TRAP_GENTRAP(0) /* Real-mode &generictrap */ addi %r1,%r1,(kern_slbtrap-generictrap) - /* 0x60 */ - mtlr %r1 + /* 0x50 */ + mtlr %r1 /* &kern_slbtrap in LR */ GET_CPUINFO(%r1) - blrl /* must fit in 128 bytes! */ + blrl /* Branch to LR, NIA in LR */ +/* must fit in 128 bytes! */ CNAME(slbtrapend): +/* + * On entry: + * SPRG1: SP + * r1: pcpu + * r2: LR + * LR: branch address in trap region + */ kern_slbtrap: std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */ std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */ @@ -527,7 +519,7 @@ kern_slbtrap: /* Check if this needs to be handled as a regular trap (userseg miss) */ mflr %r2 andi. %r2,%r2,0xff80 - cmpwi %r2,0x380 + cmpwi %r2,EXC_DSE bne 1f mfdar %r2 b 2f @@ -656,8 +648,7 @@ CNAME(alitrap): mflr %r28 /* save LR */ mfcr %r29 /* save CR */ - DMAP_ZERO(%r31) /* two instructions */ - ld %r31,TRAP_GENTRAP(%r31) + ld %r31,TRAP_GENTRAP(0) addi %r31,%r31,(s_trap - generictrap) mtlr %r31 @@ -668,7 +659,7 @@ CNAME(alitrap): /* Test whether we already had PR set */ mfsrr1 %r31 mtcr %r31 - blrl + blrl /* Branch to s_trap */ CNAME(aliend): /* @@ -691,11 +682,10 @@ CNAME(dsitrap): mfsrr1 %r31 /* test kernel mode */ mtcr %r31 mflr %r28 /* save LR (SP already saved) */ - DMAP_ZERO(%r1) - ld %r1,TRAP_GENTRAP(%r1) + ld %r1,TRAP_GENTRAP(0) addi %r1,%r1,(disitrap-generictrap) mtlr %r1 - blrl /* Branch to generictrap */ + blrl /* Branch to disitrap */ CNAME(dsiend): /* @@ -965,7 +955,7 @@ CNAME(dblow): mtlr %r1 li %r1, 0 /* How to get the vector from LR */ blrl /* Branch to generictrap */ - + /* No fallthrough */ 1: GET_CPUINFO(%r1) std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ @@ -975,10 +965,9 @@ CNAME(dblow): std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ mflr %r28 /* save LR */ - DMAP_ZERO(%r1) - ld %r1,TRAP_GENTRAP(%r1) + ld %r1,TRAP_GENTRAP(0) addi %r1,%r1,(dbtrap-generictrap) mtlr %r1 - blrl /* Branch to generictrap */ + blrl /* Branch to dbtrap */ CNAME(dbend): #endif /* KDB */