commit 7bdb87c6d81874869293afd36cf430513ea21c16
Author: Brandon Bergren <git@bdragon.rtk0.net>
Date:   Mon Dec 9 13:48:10 2019 -0600

    Testing jhibbits book-e tlb changes.

diff --git a/sys/powerpc/booke/pmap.c b/sys/powerpc/booke/pmap.c
index 805e3a691b9..cf38913d82c 100644
--- a/sys/powerpc/booke/pmap.c
+++ b/sys/powerpc/booke/pmap.c
@@ -2617,7 +2617,8 @@ mmu_booke_activate(mmu_t mmu, struct thread *td)
 	CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
 	PCPU_SET(curpmap, pmap);
 	
-	if (pmap->pm_tid[cpuid] == TID_NONE)
+	if (pmap->pm_tid[cpuid] == TID_NONE ||
+	    tidbusy[cpuid][pmap->pm_tid[cpuid]] != pmap)
 		tid_alloc(pmap);
 
 	/* Load PID0 register with pmap tid value. */
@@ -4255,8 +4256,6 @@ static void
 tid_flush(tlbtid_t tid)
 {
 	register_t msr;
-	uint32_t mas0, mas1, mas2;
-	int entry, way;
 
 
 	/* Don't evict kernel translations */
@@ -4277,31 +4276,16 @@ tid_flush(tlbtid_t tid)
 		mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT);
 		/* tlbilxpid */
 		__asm __volatile("isync; .long 0x7c200024; isync; msync");
-		__asm __volatile("wrtee %0" :: "r"(msr));
-		return;
+	default:
+		mtspr(SPR_MMUCSR0, MMUCSR0_L2TLB0_FI);
+		while ((mfspr(SPR_MMUCSR0) & MMUCSR0_L2TLB0_FI) != 0)
+			__compiler_membar();
+		/* Erase everything after TID 0 */
+		bzero(__DEVOLATILE(struct pmap **, &tidbusy[PCPU_GET(cpuid)][1]),
+		    nitems(tidbusy[0]) - 1);
+		PCPU_SET(booke.tid_next, 1);
 	}
 
-	for (way = 0; way < TLB0_WAYS; way++)
-		for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
-
-			mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
-			mtspr(SPR_MAS0, mas0);
-
-			mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
-			mtspr(SPR_MAS2, mas2);
-
-			__asm __volatile("isync; tlbre");
-
-			mas1 = mfspr(SPR_MAS1);
-
-			if (!(mas1 & MAS1_VALID))
-				continue;
-			if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid)
-				continue;
-			mas1 &= ~MAS1_VALID;
-			mtspr(SPR_MAS1, mas1);
-			__asm __volatile("isync; tlbwe; isync; msync");
-		}
 	__asm __volatile("wrtee %0" :: "r"(msr));
 }